The technical field of this invention is solid state integrated circuit fabrication and, more particularly, methods and systems for fabricating programmable interlayer conductive paths in integrated circuits.
The rapid development of large scale integrated circuitry during the past two decades has been the result of advances in both circuit design and fabrication technology, which have allowed more circuits to be implemented on a chip. A single chip can now contain hundreds of thousands of transistors, a considerable increase over the few thousand on a chip as recently as the early 1970's.
Solid state integrated circuits are typically formed from wafers, which include a plurality of layers of conductors, active electronic devices, and passive insulators on, or within, a single semiconductor crystal. After the wafer is fabricated, it can be sliced into individual chips capable of performing discrete electronic tasks.
In this technology, an interlayer conductive path through intervening insulation between conductors in the integrated circuit is called a "via". A similar path through such insulation between an overlaying conductor and a semiconductor region is called a "contact cut" (or, more descriptively, a "contact connection"). Typical wafers can have millions of such conductive paths and even moderate scale chips, containing, for example, 4,000 transistors, can have as many as 1,000 vias and over 8,000 contact connections.
Design limitations imposed by these interlayer electrical connections play an important role in present and future semiconductor circuit packing density. Very large scale integrated circuits ("VLSI") will require improved multi-level interconnects to attain performance and density goals. In theory, a three-level-metal integrated circuit permits approximately a doubling of the packing density over a two-level-metal device of similar materials and size. Device packing density, however, does not rise linearly with the increase in number of interconnected layers, but is limited by topographical area of a wafer which must be devoted to providing vias and contact cuts.
A conventional approach to constructing vias is evaporative or sputter deposition of metal into vertical directed holes. A hole is etched in an insulative layer deposited on a lower conductor, both of which overlay a substrate. A metal (which will form the overlying upper conductor) is then deposited to cover the inside and bottom of the hole and thereby establishing a conductive via through the insulative layer between the lower and upper conductors. A contact connection is fabricated in a similar way by etching a hole in which metal is deposited to provide electrical connection between an upper conductor and an underlying semiconductor region. (In practice, after the holes are etched, metal is deposited over the entire surface of the wafer and then masked and etched away selectively to leave conductive metal lines which pass over the metal-filled vias and contact cuts).
Difficulties are often encountered in preparing a clean hole and in depositing the metal for the interlayer conductive path. For example, when the metal is deposited into a hole, the metal tends to build up and form a marginal step at the top rim of the hole, before sufficient metal is deposited to reach the bottom of the hole.
Additionally, at the center of the via, a crater is formed as the metal initially conforms to the sidewalls and bottom of the hole. The result is a very irregular top surface of the via. This condition can lead to thinning of the upper conductor, as well as non-planar deposition of subsequent layers, in the region immediately above the via.
Moreover, the planar irregularities can cause distortions in photo-resists and subsequent layers of integrated circuitry deposited above the via. When a photoresist is deposited above a via (or an intermediate non-planar surface such as a metal conductor), the exposing light during development can be reflected by the underlying contour and lead to the narrowing or notching of the photoresist or subsequent deposits, thereby imposing limits on the resolution of device and conductor structures in these layers.
The problems associated with step coverage over vias has led to VLSI design rules which prohibit the deposition of other metal conductors directly above any via. The process of forming vias by etching holes also requires a widening of the interconnected conductors at least in the area of each via to ensure that each hole is surrounded by sufficient metal to provide tolerance in the vertical registration of conductors.
For example, a two micron wide conductor is required for a one micron wide via, and, similarly, a one micron wide conductor is needed for a 1/2 micron wide via to assure sufficient overlap.
At very small dimensions, it becomes increasingly difficult to ensure continuity and integrity of vias and contact cuts. One reason for this is the difficulty at such dimensions to clean out the bottom of the hole H of all insulating material prior to metal deposition. Another is the difficulty of depositing metal into such small holes.
The problem of getting metal down into the via or contact cut can be reduced by forming the hole with sloping sides. However, a vertical conductive path with sloping sides obviously takes up more space on the wafer and, as the need for smaller and smaller device structures continues, the less attractive this solution becomes. It has been estimated that with conventional via design, it will be difficult to reduce the area occupied by the via below 2.times.2 microns. Furthermore, steep sloping sides can make it difficult to deposit a sufficiently thick uniform conductive film on the sides of the holes.
An alternative process for filling vias is to fill the holes by chemical vapor deposition ("CVD") rather than by the evaporative or sputter deposition of metal over the entire surface of the wafer. In CVD processes it is possible to selectively grow metal layers over only those regions of the wafer where metal is already exposed. In this manner a via can be filled up from the bottom by selective deposition of a metal such as tungsten. However, even the most promising of the CVD processes are difficult to control, particularly when filling contact cuts, and, in any event, a hole still must be cut and then fully cleaned out before the metal can be deposited.
Another approach involves the use of lasers to convert an insulator into a conductor and thereby forming the interlayer path. Commonly owned U.S. Pat. Nos. 4,585,490 and 4,810,663 disclose a technique in which a "link insulator" is deposited where vias are desired. When a metal layer deposited above the link insulator is exposed to a high power laser having a pulse on the order of about 1 millisecond, a conductive path can be formed by melting the top metal layer and alloying at least a portion of it with the link insulator material. However, the deposition of link insulators involves materials such as amorphous silicon and silicon-rich silicon nitride which are not extensively used in the semiconductor industry.
The requirements associated with the formation of interlayer conductive paths by conventional techniques place limitations on the circuitry and affect circuit density. Consequently, it is an object of the invention to provide methods and systems for fabrication of integrated circuits with simpler design requirements, higher packing densities and more planar surfaces than those resulting from conventional interlayer connection technology.
In the above-referenced, commonly-owned patent applications, U.S. Ser. Nos. 194,720 and 061,885, methods and systems are disclosed for fabricating interlayer conductive paths by implanting ions into selected regions of normally insulative layers to change the composition and/or structure of the insulation in the selected regions. An upper conductive layer can then be deposited over such implantation regions and the entire structure sintered at a temperature between approximately 330.degree. C. and 500.degree. C. As a result of the low temperature sintering, atoms from the upper conductive layer or, where two conductive layers are being interconnected, from the upper and lower conductive layers, are diffused or alloyed into the implant region to form a low resistance, conductive path between the upper conductor and the underlying element, the path having a bulk resistivity of about 10.sup.-4 ohm-cm, or less.
The approach of U.S. Ser. Nos. 194,720 and 061,885 takes advantage of sintering steps which are already employed in semiconductor device fabrication for other purposes. Wafers are typically sintered to reduce the adverse effects of the various other processing steps during their fabrication and to improve electrical connections between conductors and the electronic devices throughout the wafer.
However, the sintering process is by its nature non-specific and ill-suited to the fabrication of variable or programmable circuits. The ability to selectively alter circuit paths in previously fabricated devices is very important for the production of user-customizable integrated circuits. The use of programmable vias, called links, enables the creation of such unique circuits.
There exists a need for better fabrication techniques for interlayer conductive paths, particularly paths which can be selectively activated or programmed to form customized gate arrays and other programmed devices.